`timescale 1ns / 1ps
/*--------------------------------------------------------------------*\
FileName        : cpsm_iod.v
Author          ：hpy
Email           ：yuan_hp@qq.com
Date            ：2024年07月06日
Description     ：
\*--------------------------------------------------------------------*/


`define debug(cmd) cmd 

module cpsm_io (
    input clk,
    input rst_n , 
    output reg [7:0] gpio0
);
 
/* ------------------ function -------------------- */
 
/* -------------------- param --------------------- */
 
/*---------------------- reg ---------------------- */
reg [7:0] soft_inter   =0;
reg [7:0] soft_inter_r =0;
/*----------------------- wire ---------------------*/
 
/*--------------------- assign ---------------------*/

/*---------------------- blk -----------------------*/
 
 
wire [7:0] out_port , port_id ; 
reg  [7:0] in_port ;
wire write_strobe  ;

psm6_soc #(
    .memfile("cpsm_io.hex") ,  
    .memnum ( 1024)  , 
	.stack_size  (32) ,  // 1 ~ 32 
	.scratch_size( 256) // 1 ~ 256  
) psm_soc_u1 (
    .clk (clk) ,
    .reset(~rst_n ) ,
    .in_port (in_port ),
    .out_port(out_port) ,
    .port_id (port_id ),
    .write_strobe(write_strobe) ,
    .interrupt( {soft_inter_r[0],soft_inter[0]} == 2'b01 ) ,
    .interrupt_ack()
); 


always @(posedge clk ) begin
    soft_inter_r <= soft_inter ;
end

always@ (posedge clk) begin
    if(write_strobe)begin //
        case(port_id)
            8'h00:  begin 
                gpio0  <= out_port;
                `debug($display("%t ns write gpio0:%08x",$time , out_port) );
            end 
            8'hff: begin
                soft_inter <= out_port;
            end
            default:  ;
        endcase 
    end 
end  


//输入口
always @(*)begin
    case(port_id)
        8'h00: in_port = gpio0;
        8'hff: in_port = soft_inter;
        default:in_port = 8'h00;
    endcase
end

endmodule
 
